1. Field of the Invention
The present invention relates to the field of analog storage devices. More particularly, this invention relates to a circuit and method for adjusting the voltage applied to a gate of a non-volatile memory cell to improve programming accuracy.
2. Description of Prior Art
Currently, various analog storage devices are designed with circuitry used to program non-volatile (NV) memory cells of a memory array such as Electrically Erasable Programmable Read Only Memory (EEPROM) cells. Cell programming may be accomplished by applying programming voltage to a drain of a targeted EEPROM cell in accordance to a read-while-writing voltage program technique of U.S. Pat. No. 5,629,890.
U.S. Pat. No. 5,629,890 describes the read-while-writing voltage program technique in which a voltage present on a source terminal of the EEPROM cell is provided to a comparator and compared with a selected target voltage. The selected target voltage is a slightly reduced voltage sampled from an input analog signal. So long as the selected target voltage is greater than the source voltage of the EEPROM cell, a high voltage ramp is supplied to the EEPROM cell. Once the selected target voltage has been reached, the supply of the high voltage ramp to the EEPROM cell is discontinued and a new voltage is calculated and loaded into the comparator to continue programming as needed.
It is well known that the exact electrical characteristics of NV memories, may vary in production due to variations in fabrication. For example, the coupling ratio tends to vary for EEPROM cells. The "coupling ratio" is a ratio of (i) the capacitance between a floating gate and a drain terminal of the floating gate transistor and (ii) the capacitance between the floating gate and a control gate. While the read-while-write voltage program technique tolerates many electrical characteristic variations, it remains vulnerable to variations in the coupling ratio. Such vulnerability occurs when a predetermined, generally constant voltage is applied to the control gate.
More specifically, as greater voltage is applied to the drain terminal of the floating gate transistor, this inadvertently causes an increase in voltage at the source terminal (source voltage). Since this source voltage is measured during the read-while-write voltage program technique to detect when to discontinue programming of the EEPROM cell, cell programming may be discontinued prematurely causing the EEPROM cell to be under-programmed. During a normal read operation, when the difference between the selected target voltage and the voltage of the EEPROM cell is determined in order to calculate a new target voltage, this new target voltage will be artificially large, not a small incremental voltage as intended. In fact, since the programming of EEPROM cells is an iterative process, the source voltage measured during the read-while-write voltage program technique will become impractically large where the target voltage can be greater than the supply voltage provided by a power supply.
Since variations in EEPROM fabrication techniques cause variation in capacitive coupling between the floating gate and the drain terminal, a standard adjustment of voltage applied to the control gate may cause inaccurate programming of EEPROM cells in certain situations. For multi-level analog voice applications, reduced accuracy appears as noise or distortion. For multi-level voltage used for digital storage, this reduced accuracy causes either errors or a reduction in the number of distinct levels which can be used per EEPROM cell. As a result, it would be desirable to develop and implement a voltage control circuit to control the compensation of ramp voltage applied to the control gate to mitigate undesirable changes in source voltage.